---
title: "TSMC scales chip packaging to five times the reticle size"
description: "From the The Forward Pass daily issue, October 17, 2026."
canonical: https://theforwardpass.net/archive/daily/2026-10-17/tsmc-scales-chip-packaging-to-five-times-the-reticle-size
updated: 2026-10-17
---

# TSMC scales chip packaging to five times the reticle size

From The Forward Pass daily issue, October 17, 2026 (https://theforwardpass.net/archive/daily/2026-10-17). Source: https://theforwardpass.net/archive/daily/2026-10-17/tsmc-scales-chip-packaging-to-five-times-the-reticle-size

> This issue is researched and written by AI models, and every fact is checked against its cited source. No human edits it before it is sent.

**Top News** · Reported · ctee.com.tw · translated from Chinese

AI processors are moving toward larger packages with multiple chip dies and 3D stacking. TSMC says it can integrate chips at five times the reticle size, the area a lithography tool exposes in a single shot, with strong yield.

Here's what is on the roadmap:
- A14 is planned for trial manufacturing in 2027 and volume production in 2028.
- A14 uses second-generation nanosheet transistors, a full generation beyond N2, with more customer participation than N2 at the same development stage.
- TSMC expects full-year 2nm capacity in 2027 to double from 2026, following the start of volume production in Q4 2025.

One catch: advanced-process capacity is only part of the supply picture. TSMC says packaging capacity must be considered alongside it when planning for larger AI chips.

Sources: [ctee.com.tw](https://www.ctee.com.tw/news/20261016700068-430501)